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Results: 1614

#	Item
741	Digital Semiconductor[removed]Core Logic Chipset Technical Reference Manual Order Number: EC–QUQJA–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:28 Conventional PCI PCI configuration space PCI Express Memory-mapped I/O CPU cache Cell Translation lookaside buffer Direct memory access IOMMU Computer hardware Computer buses Computing
742	Microsoft Word - s3-0.8-zw.docx Add to Reading List Source URL: www.owlnet.rice.edu Language: English - Date: 2011-07-19 12:45:45 Data World Wide Web Web browser Information Hypertext Transfer Protocol CPU cache Cache Computing Web cache
743	Profile-Based Energy Reduction for High-Performance Processors Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:52:52 Computer architecture Profilers Software optimization CPU cache Cache Computer memory Profiling Program optimization Microarchitecture Computing Computer hardware Central processing unit
744	Alpha[removed]EV67 Microprocessor Hardware Reference Manual Order Number: DS–0028C–TE This manual is directly derived from the internal[removed]EV67 Specifications, Revision 1.5. You can access this hardware reference m Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:51 Computer engineering DEC Alpha Alpha 21264 PALcode CPU cache Processor register Instruction set Computer architecture Computer hardware Central processing unit
745	Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization ´ Garzar´an, Lawrence Rauchwergery , and Josep Torrellas Milos Prvulovic, Mar´ıa Jesus University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-23 12:50:54 Computer memory Cache coherency Central processing unit CPU cache Cache Multi-core processor Speedup Automatic parallelization Memory hierarchy Computing Parallel computing Computer architecture
746	OmniOrder: Directory-Based Conflict Serialization of Transactions ∗ Xuehai Qian † University of California, Berkeley Benjamin Sahelices Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-04-19 12:44:14 Computer hardware Computer memory CPU cache MESI protocol MSI protocol Cache Transactional memory Parallel computing Cache coherency Computing Concurrent computing
747	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 00:54:20 Central processing unit Runahead CPU cache Microprocessors Branch predictor Memory-level parallelism Microarchitecture Instruction window Hardware scout Computer architecture Computer hardware Computer engineering
748	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection∗ Abdullah Muzahid, Norimasa Otsuki† , and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-10-23 11:07:53 Data Transaction processing Computer memory Parallel computing Linearizability CPU cache I1 Cache Q Computing Data management Concurrency control
749	AlphaPC64 Evaluation Board User’s Guide Order Number: EC–QGY2C–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:06 Conventional PCI PCI configuration space PCI Express Expansion card DEC Alpha Bus CPU cache PCI-X Alpha 21064 Computer buses Computer hardware Computing
750	The Stanford Hydra CMP Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Michael Chen, Maciek Kozyrczak, and Kunle Olukotun Computer Systems Laboratory Stanford University http://www-hydra.stanford.edu Add to Reading List Source URL: www-hydra.stanford.edu Language: English* - Date: 1999-11-05 21:09:40 Computer architecture CPU cache Cache Central processing unit Multi-core processor Parallel computing Direct memory access Harvard architecture Computer hardware Computing Computer memory

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